Abstract: FPGA architectures have undergone repeated redesign cycles, shaped by the relentless pressure of semiconductor limits, shifting market demands, and the practicalities of deployment. While certain architectural concepts have successfully scaled across generations, others have faltered despite some initial promise.

In this keynote, we will examine the historical trajectory of FPGA performance and power metrics, but we will ultimately argue that cost in its many dimensions is the ultimate architect. We will explore how the “invisible hand” of cost has quietly dictated the evolution of logic fabrics, routing complexity, and the strategic integration of hardened IPs. From silicon floorplans to the inherent complexities of software toolchains, successful innovation has consistently hinged on finding the optimal economic and technical trade-offs.

By extracting these durable lessons, we can better navigate the next decade of reconfigurable computing. We will examine how a cost-centric mindset – one that balances area, power, development time, and software friction – remains our most powerful tool for uncovering new opportunities for FPGAs in an increasingly complex semiconductor landscape.

CV: Ilya Ganusov is Chief Silicon Architect at Altera, leading FPGA architecture definition and long term architectural research across core fabrics, memory and interconnect architectures, and architectural methodologies under real world power and performance constraints. He joined Intel’s FPGA organization in 2018, where he led the Agilex™ FPGA core architecture and application driven optimizations for AI, high performance computing, wireless communications, and real time systems. Prior to Intel and Altera, he held senior architecture roles at Xilinx, contributing to multiple FPGA generations, and at Achronix, working on asynchronous FPGA architectures. Ilya has co authored more than 40 granted patents and numerous publications on FPGA architectures, CAD algorithms, memory systems, and circuit design. He holds a Ph.D. in Electrical and Computer Engineering from Cornell University.

Abstract: AI inference refers to the process of applying a trained artificial intelligence model to analyze new data and generate predictions in real-time. Unlike the training phase, which requires extensive computational resources, inference must be efficient, low-latency, and power-conscious—especially in embedded systems with strict hardware constraints.
FPGA-based AI inference presents unique advantages, including reconfigurability, parallel processing capabilities, and post-production hardware specialization. However, these benefits come with trade-offs related to Performance, Latency, Area, and Power, as well as the need for an optimized AI inference tool flow.
This talk explores how adaptive FPGA architectures enhance AI inference through hardware-software co-design. Using a constraint-driven methodology, we compare inference approaches across CPUs, GPUs, AI accelerators, NPUs (DPUs), vector extensions, and embedded inference frameworks like FINN. Our analysis identifies FPGA-optimized AI solutions that improve performance scalability while minimizing size and power consumption, ensuring adaptability and compatibility with standardized inference workflows.
Looking ahead, AI inference on embedded FPGAs is expected to play a key role in next-generation systems.

CV: Tryggve earned a MSc CSE from CTH Gothenburg in 1987. He has deep system engineering background in computer arithmetic, application acceleration and systems design using FPGAs. As an FPGA and system expert in Industrial, Automotive and Telecommunication fields, he has enabled complex embedded systems and educated customers in FPGA design. The last 8 years at AMD/Xilinx, the current focus lies in advancing AMD customers embedded system design and utilization of neural-network inference solutions.