Abstract: FPGA architectures have undergone repeated redesign cycles, shaped by the relentless pressure of semiconductor limits, shifting market demands, and the practicalities of deployment. While certain architectural concepts have successfully scaled across generations, others have faltered despite some initial promise.
In this keynote, we will examine the historical trajectory of FPGA performance and power metrics, but we will ultimately argue that cost in its many dimensions is the ultimate architect. We will explore how the “invisible hand” of cost has quietly dictated the evolution of logic fabrics, routing complexity, and the strategic integration of hardened IPs. From silicon floorplans to the inherent complexities of software toolchains, successful innovation has consistently hinged on finding the optimal economic and technical trade-offs.
By extracting these durable lessons, we can better navigate the next decade of reconfigurable computing. We will examine how a cost-centric mindset – one that balances area, power, development time, and software friction – remains our most powerful tool for uncovering new opportunities for FPGAs in an increasingly complex semiconductor landscape.

CV: Ilya Ganusov is Chief Silicon Architect at Altera, leading FPGA architecture definition and long term architectural research across core fabrics, memory and interconnect architectures, and architectural methodologies under real world power and performance constraints. He joined Intel’s FPGA organization in 2018, where he led the Agilex™ FPGA core architecture and application driven optimizations for AI, high performance computing, wireless communications, and real time systems. Prior to Intel and Altera, he held senior architecture roles at Xilinx, contributing to multiple FPGA generations, and at Achronix, working on asynchronous FPGA architectures. Ilya has co authored more than 40 granted patents and numerous publications on FPGA architectures, CAD algorithms, memory systems, and circuit design. He holds a Ph.D. in Electrical and Computer Engineering from Cornell University.

Abstract: Security in FPGAs didn’t arrive as a monolith. It evolved across generations as we learned what attackers cared about and what users needed. This talk traces that evolution from our antifuse roots, through authenticated configuration and side channel resistant provisioning, to today’s layered, defense grade feature sets that make security a built in property rather than an add on.
Along the way we’ll share compact, technical stories that changed our trajectory, like the polite note from an independent lab demonstrating device key extraction via differential power analysis. That single data point galvanized a shift to DPA resistant cryptography and third party evaluation, and it shaped how we think about key storage, tamper response and zeroization.
Attendees will leave with a practical timeline of “what, why, and how” of authenticated bitstreams, DPA hardened flows, PUF anchored key custody, tamper sensors with deterministic zeroize and secure provisioning chains and guidance on when each control matters. It’s a candid, engineering level look at how trustworthy FPGAs are built and how those lessons transfer to your next design.

CV: Martin Kellermann is a Marketing Manager at Microchip Technology GmbH, Munich. In this role he works with the European Sales and Field Application team to position the strengths of Microchip FPGAs and SoCs to clients.
He is a seasoned FPGA and SoC professional with a track record of successful customer and project engagements in the industrial, automotive, and data-center domains. Martin possesses a strong background in high-speed serial data transmission, signal integrity and hardware debugging which helped numerous customers finish their designs successfully. He has also taught courses covering industrial applications and hardware concepts. Martin holds a diploma on Electrical Engineering from the Landshut University of Applied Sciences.